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A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

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3 Author(s)
Jui-Yuan Yu ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu ; Ching-Che Chung ; Chen-Yi Lee

This work addresses power reduction and performance improvement for wireless orthogonal frequency-division multiplexing (OFDM) systems using a dynamic sample-timing controller (DSTC) and phase-tunable clock generator (PTCG). The receiver, applying the proposed DSTC algorithm, searches for the optimal sampling phase at the symbol rate, instead of the Nyquist rate (or higher), to reduce the extra power consumed in high-rate operations. The proposed PTCG circuits provide the desired clock phase for optimum sampling to improve system performance. Both the DSTC and the PTCG are evaluated in a multiband OFDM (MB-OFDM) ultra-wide-band system. Simulation results indicate that the overall system performance is improved by 1.7-dB signal-to-noise ratio at a packet error rate of 8% and the total baseband power is reduced by 40%.

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:55 ,  Issue: 9 )