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A Time-Interleaved \Delta \Sigma -DAC Architecture Clocked at the Nyquist Rate

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2 Author(s)
Jennifer Pham ; Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON ; Anthony Chan Carusone

This paper describes a delta-sigma (DeltaSigma) digital-to-analog converter (DAC) architecture that combines a polyphase decomposition of the interpolation filter and a time-interleaved error-feedback DeltaSigma modulator. Noise-shaped oversampling is achieved while clocking the digital circuitry at the Nyquist rate. The design of a third-order 4-bit modulator with eight times oversampling using the architecture is presented. Results from a prototype current-DAC driven by a VHDL simulation of the digital design at 2.66 GHz show that 56-dB linearity is achievable in 90-nm CMOS within a 1-V supply over a 155-MHz signal bandwidth making the architecture suitable for emerging ultra-wide-band and 60-GHz radio applications.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:55 ,  Issue: 9 )