By Topic

Reconstructing Control Flow in Modulo Scheduled Loops

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Miao Wang ; Inst. of Inf. Sci. & Technol., Zhengzhou ; Rongcai Zhao ; Jianmin Pang ; Guoming Cai

Software pipelining is a loop optimization technique used to exploit instruction level parallelism in the loop. EPIC architectures, such as Intel IA-64 (Itanium) provide extensive hardware support for software pipelining to generate compact and highly parallel code. However it transforms explicit conditional branches into implicit control flow based on the information of the guard registers. It is difficult to reconstruct precise control flow from the optimized code. This paper describes an approach to reconstruct implicit control flow in modulo scheduled loops and thereby improve the quality of reverse engineering optimized executables. We also demonstrate the effectiveness of this approach through experiment results.

Published in:

Computer and Information Science, 2008. ICIS 08. Seventh IEEE/ACIS International Conference on

Date of Conference:

14-16 May 2008