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The use of a two-phase clocking scheme and charge transfer switches leads to increased power efficiency in on-chip voltage elevators, but also to leakage currents in the presence of non-ideal control signals. This paper presents a simple model to predict the amount of leakage current (and, thus, of output voltage loss) in the presence of a given skew time between the two phase clocks. The nonlinear dependence of leakage on the load current and the impact of skew time over output voltage is highlighted. Simulations in 0.13-mum CMOS technology confirm the validity of the model.