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In 65nm and smaller technologies, Vmin fails account for a substantial portion of the total fails seen in memories. Redundancy has traditionally been used to fix random point defects which can be modeled with Critical Area Analysis. As technologies migrate from 90 nm to 65nm, cost optimization requires consideration of Vmin yield fallout as well as random defects when selecting a SRAM memory redundancy scheme. Since added redundancy requires additional silicon area, redundancy schemes need to be balanced against the cost required to enable memory repairs.