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A cost effective system-on-a-chip (SOC) test strongly hinges on the parallel independent test of SOC cores, which can only be ensured through proper core isolation techniques. Whereas a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed coverage on the core interface. In this paper, we provide an in-depth analysis of the soft core isolation problem by covering a wide spectrum of techniques ranging from the utilization of only functional registers to the utilization of only wrapper cells. We model the generalized problem of finding the minimum number of isolation registers, in the form of a mixture of functional registers and wrapper cells, by mapping the problem onto the maximum Boolean satisfiability problem; by utilizing the key findings in this mapping, we implement a computationally efficient heuristic for selecting a subset of core I/Os, on which wrapper cell insertion minimizes the total number of interface registers. Finally, we demonstrate the application of this heuristic, with area and performance constraints also accounted for, delivering a wide spectrum of tradeoff points for isolating a soft core.