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Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

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8 Author(s)
Vitullo, F. ; Dept. of Inf. Eng., Univ. of Pisa, Pisa ; L'Insalata, N.E. ; Petri, E. ; Saponara, S.
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Clock distribution is an important issue when designing Multi Processor Systems-on-Chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a Multi Processor tiled architecture based on a Network-on-Chip communication backbone on a CMOS 65 nm technology

Published in:

Computers, IEEE Transactions on  (Volume:57 ,  Issue: 9 )

Date of Publication:

Sept. 2008

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