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Dual- V_{dd} Buffer Insertion for Power Reduction

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5 Author(s)
King Ho Tam ; Electr. Eng. Dept., Univ. of California, Los Angeles, CA ; Yu Hu ; Lei He ; Tom Tong Jing
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This paper presents the first in-depth study on dual-Vdd buffer insertion for power minimization under delay constraint. Compared with delay-optimal single Vdd buffer insertion, the dual- Vdd buffer insertion reduces power by 16%. Such power reduction increases when the delay specification is relaxed. Whereas the van Ginneken algorithm can be extended to handle the new problem formulation optimally, its time complexity increases from quadratic time (O(|B|n 2)) to pseudopolynomial time (O(|B|n 3 c max 2log(nc max)), where |B| is the size of buffer library, n is the number of buffer stations, and c max is proportional to the number of all possible subtrees of the net. To improve the time complexity, we propose an approximation technique by sampling subsolutions (i.e., options) and apply predictive min-delay and prebuffer slack pruning rules from a related work. Experiments show that sampling is most effective to reduce run time, whereas the two pruning rules further improve efficiency and accuracy loss due to sampling. We show that our proposed algorithm has linear time complexity with respect to the tree size. It runs over 1000 times faster at a cost of less than 2% delay and power increase over the extended van Ginneken algorithm.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:27 ,  Issue: 8 )