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Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures

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3 Author(s)
Chatha, K.S. ; Dept. of Comput. Sci. & Eng., Arizona State Univ., Tempe, AZ ; Srinivasan, K. ; Konjevod, G.

This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target device. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis approach consisting of the following: (1) core to router mapping and (2) custom topology and route generation. In particular, it presents an optimal technique for core to router mapping [stage (1)] and a factor-2 approximation algorithm for custom topology generation [stage (2)]. The superior quality of the techniques is established by experimentation with benchmark applications and by comparisons with existing approaches.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:27 ,  Issue: 8 )