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Trapped-Hole-Enhanced Erase-Level Shift by FN-Stress Disturb in Sub-90-nm-Node Embedded SONOS Memory

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5 Author(s)
Terai, M. ; Device Platforms Res. Labs., NEC Corp., Sagamihara ; Tsuji, Y. ; Kotsuji, S. ; Fujieda, S.
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The amount of FN-disturb-induced erase-level shift in a sub-90-nm-node embedded polysilicon/oxide/nitride/oxide/silicon-type trap memory was found to peak at 25degC to decrease briefly at 90degC and then to increase again at higher temperatures. This characteristic temperature dependence can be explained by three processes. First, electrons are injected from the substrate into the nitride layer through traps in the bottom oxide (BOX). Second, holes that are trapped in the BOX during program/erase cycles increase the electric field in the BOX near the substrate, thus enhancing the effect of the electron injection. Third, this enhancement is weaker at elevated temperatures because of hole emission from the BOX. We propose empirical fitting equations for describing the FN-disturb behavior, which consider the effects of traps and holes within the BOX. Moreover, we show that the effect of nitriding the BOX layer on FN-disturb immunity results from a decrease in the trap density of the BOX.

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Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 6 )