Finite-Element Computation of Sensitivities of Interconnect Parasitic Capacitances to the Process Variation in VLSI

As the VLSI technologies shrink to nanoscale, the process variability has become a critical issue: what we get on silicon is substantially different than what we design. Dealing with the process variation is an important subject in today's integrated circuit (IC) design, modeling, and simulation. Sensitivity analysis turns out to be an efficient tool to address this kind of issue. This paper uses the finite-element method to compute the parasitic capacitances of IC interconnects based the nominal geometry parameters, and the capacitance sensitivities with respect to the geometry parameters susceptible to vary. The goal of sensitivity computation using the finite-element method is to compute the first derivative of unknown vectors with respect to the geometry parameters. In contrast to the traditional differential method, this method reduces the error and the compute time. This paper makes a useful attempt in the aspect of using sensitivities to analyze the certain and the uncertain variation of geometry parameters of IC interconnects.