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A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM

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4 Author(s)
M. Gunhan Ertosun ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Hoon Cho ; Pawan Kapur ; Krishna C. Saraswat

We experimentally demonstrate and characterize a vertical (current flow that is perpendicular to the wafer) source (bottom)/drain (top) double-gate capacitorless single-transistor DRAM on a bulk silicon wafer. We have electrically measured retention times in excess of 25 ms. Device fabrication was facilitated by several key process innovations, which allow the device to also be integrated with planar devices using minimal additional process steps. The structure results in a highly scalable DRAM down to 22-nm technology node.

Published in:

IEEE Electron Device Letters  (Volume:29 ,  Issue: 6 )