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Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering

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8 Author(s)
Fujiwara, H. ; Grad. Sch. of Sci. & Technol., Kobe Univ., Kobe ; Nii, K. ; Noguchi, H. ; Miyakoshi, J.
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We propose a low-power two-port SRAM for real-time video processing that exploits statistical similarity in images. To minimize the discharge power on a read bitline, a majority-logic circuit decides if input data should be inverted in a write cycle, so that ldquo1rdquos are in the majority. In addition, for further power reduction, write-in data are reordered into digit groups from the most significant bit group to the least significant bit group. The measurement result of a 68-kbit video memory in a 90-nm process demonstrates that a 45% power saving is achieved on the read bitline. The speed and area overheads are 4% and 7%, respectively.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:16 ,  Issue: 6 )