By Topic

Ball Grid Array (BGA) Solder Joint Intermittency Detection: SJ BIST

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Hofmeister, J.P. ; Ridgetop Group, Inc., Tucson, AZ ; Lall, P. ; Roth, N.N. ; Tracy, T.A.
more authors

This paper presents test results and specifications for SJ BISTTM, an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well-known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults of 100 Omega or lower with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock; guaranteed detection is two clock periods. Being able to detect solder joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.

Published in:

Aerospace Conference, 2008 IEEE

Date of Conference:

1-8 March 2008