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This paper describes issues and tradeoffs related to the design of undersampling delta-sigma modulators (DeltaSigmaMs) for wireless receivers. It proposes a new bandpass undersampling DeltaSigmaM architecture dedicated to multigigahertz frequencies. This paper is based on up-sampling in the feedback path to remove the analog mixer usually found in the modulator. Design equations are discussed for an optimum operating point when the input signal is at 1.8 GHz. The related design model can be applied to many communication standards. The underlying proposed architecture can receive high-frequency carriers modulated with signals of bandwidth as large as 5 MHz. In the proposed design, it converts the signal into digital data with a spurious-free dynamic range of 46 dB at a sampling frequency of 810.1 MHz. Design simulation, characterization, and implementation of the proposed modulator are done using a 0.13- mum CMOS technology.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:55 , Issue: 11 )
Date of Publication: Dec. 2008