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Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism

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3 Author(s)
Chia-Yu Lin ; Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei ; Mong-Kai Ku ; Yi-Hsing Chien

In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with quasi-cyclic (QC) LDPC codes at long block lengths. A modified progressive edge-growth algorithm is used to construct the hierarchical quasi-cyclic (H-QC) LDPC codes. By adding implementation-friendly two-level hierarchy with limited types of second-level submatrices in the parity check matrix, coding performance is improved substantially over QC codes. We also show that QC-based decoder architecture can be easily applied to H-QC decoders to achieve better coding gain and higher throughput performance. Moreover, the degree of decoding parallelism and code length can be adjusted by changing the H-QC code construction parameters.

Published in:

Vehicular Technology Conference, 2008. VTC Spring 2008. IEEE

Date of Conference:

11-14 May 2008