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The general tendency of the portable handheld electronic is to integrate more and more functionalities (phone, audio, video, Internet, wireless connections, etc.) in a size that is smaller and smaller (thinner devices per example). Thus, electronic components with a great level of miniaturization are needed, like wafer level chip scale packages (WL-CSP), to answer the market demand. In order to cover a wide range of flip chips, the test vehicle used in this study is a daisy chain with a matrix of 5times5 and a pitch of 500 mum. The reliability of this package has been studied by employing the JEDEC JESD22-B111 standard drop test. In this paper, the JEDEC B-condition is applied to the vehicle test. The board and the JEDEC procedure are presented in details. The results interpretation is assured by statistical distributions and failure analysis. A drop impact life model (input-G model) is established for the drop test simulation of WL-CSP. It is a powerful tool because it is able to give a good qualitative understanding of physical aspects involved in drop test failures of the WL-CSP. Indeed, it permits to locate the critical bumps, the stress level and the initiation of cracks mainly at the bump/die interface. The correlation between the dynamic simulation and experiment results is very good. The failures analysis revealed that the main failure modes in the component side are crack in the intermetallic layer and cracks in the passivation layer. An other failure mode is detected at the board side but it can not be recorded as defect. The fact that cracking occurs predominantly at the component side is due to three factors: higher peeling stress Sz at the component side, the brittleness of intermetallics and the strain-rate hardening of the bumps.