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Thermo-mechanical simulations for 4-layer stacked IC packages

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2 Author(s)
Ming-Che Hsieh ; EOL/Industrial Technology Research Institute, Rm.168, Bldg.14, No.195, Sec. 4, Chung Hsing Rd., Chutung, Hsinchu, 310 Taiwan, R.O.C. ; Chih-Kuang Yu

Since the shortened wiring length between devices and chips in stacked IC package can reduce the signal delayed effects and improve many electrical characteristics, the topics of stacked IC package are now being studied extensively. Although the electrical benefits are greatly increasing in stacked IC packages, their corresponding thermo-mechanical problems are raising as well, including the problems of heat dissipation, induced stresses, interfacial delamination, via cracking and so on. These problems always cause failures or fatigues in stacked IC packages and become critical reliability issues. In order to obtain thermal and stress distributions in stacked IC packages, the 4-layer stacked IC package (chip on chip) with TSV (through silicon vias) structure has been constructed as our test vehicle in this paper. Not only the temperature distributions but also the junction temperature and thermal resistances in 4-layer stacked IC package have been obtained. In addition, the thermal induced stress distributions in the same structure have also been illustrated. Further, for the purpose of studying the sensitivities of material properties of underfill, the response surface methodology (RSM) has been adopted. By RSM, the optimum material properties of underfill and this result in smaller von Mises stresses in their composite parts can be obtained. These results will be useful design guidelines to engineers when optimum stress and/or thermal solutions in 4-layer stacked IC package are demanded.

Published in:

Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems, 2008. EuroSimE 2008. International Conference on

Date of Conference:

20-23 April 2008