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IBM z10: The Next-Generation Mainframe Microprocessor

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1 Author(s)
Webb, C.F. ; IBM, Poughkeepsie, NY

The IBM system z10 includes four microprocessor cores - each with a private 3-Mbyte cache - and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10's CPU performance.

Published in:

Micro, IEEE  (Volume:28 ,  Issue: 2 )

Date of Publication:

March-April 2008

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