By Topic

A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Shimizu, Y. ; Sony LSI Design, Nagasaki ; Murayama, S. ; Kudoh, K. ; Yatsuda, H.

The ADC is fabricated in 90 nm digital CMOS process. The chip consumes 34 mW at 300MS/s (fin=fs/2) from 1.2 V analog/digital and 2.5 V T/H-switches supply. At 100 MS/s (fin= fs/2), it consumes 6.7 mW from 0.75 V analog/digital and 1.5 V T/H-switches supplies. FOMs are 780 fJ/conversion-step at 300 MS/s (fin=fs/2), 680fJ/conversion-step at 300MS/s (fin=2MHz), 350 fJ/conversion- step at 100 MS/s (fin=fs/2) and 290 fJ/conversion-step at 100 MS/s (fin=2MHz).The active area is 0.29 mm2.

Published in:

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Date of Conference:

3-7 Feb. 2008