A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS

The ADC is fabricated in 90 nm digital CMOS process. The chip consumes 34 mW at 300MS/s (f
_in
=f
_s
/2) from 1.2 V analog/digital and 2.5 V T/H-switches supply. At 100 MS/s (f
_in
= f
_s
/2), it consumes 6.7 mW from 0.75 V analog/digital and 1.5 V T/H-switches supplies. FOMs are 780 fJ/conversion-step at 300 MS/s (f
_in
=f
_s
/2), 680fJ/conversion-step at 300MS/s (f
_in
=2MHz), 350 fJ/conversion- step at 100 MS/s (f
_in
=f
_s
/2) and 290 fJ/conversion-step at 100 MS/s (f
_in
=2MHz).The active area is 0.29 mm
²
.