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Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies

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15 Author(s)

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.

Published in:

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

Date of Conference:

3-7 Feb. 2008