Referenced Items are not available for this document.
We present an 8 MB/s 3-bit per cell (D3) NAND flash memory that uses the same number of ECC bytes as 2-bit per cell (D2) NAND. Since no extra columns are added in D3 devices, the 16 Gb D3 chip in this paper achieves 0.112 Gb/mm2 compared to 0.079 Gb/mm2 on D2 chips, as previously reported (K. Takeuchi et al.,2006). This is a 41% improvement in Gb/mm2 and a 20% gain in overall die-size.
Published in:
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Date of Conference: 3-7 Feb. 2008
- Page(s):
- 506 - 632
- E-ISBN :
- 978-1-4244-2011-7
- Print ISBN:
- 978-1-4244-2010-0
- INSPEC Accession Number:
- 10047976
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2008.4523279
- Product Type:
- Conference Publications
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