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This paper describes a 60 GHz-band (output) frequency tripler with I/Q outputs implemented in a production 90 nm CMOS technology . Differential quadrature outputs with high phase accuracy and low amplitude error are required for single-sideband frequency translation. Regenerative peaking reduces power consumption and optimizes the response of the 50 Omega output buffer. The tripler can relax requirements on the design of the PLL synthesizer, as a fundamental (i.e., 60GHz) VCO and high-speed dividers, which may consume more power and compromise performance, are not required. It should be noted that the tripler operating frequency can be selected to fit the desired transceiver architecture and frequency plan.
Date of Conference: 3-7 Feb. 2008