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A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology

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10 Author(s)

We report a 153Mb SRAM design that is optimized for a 45nm high-K metal-gate technology (Mistry et al., 2007). The design contains fully integrated dynamic forward-body-bias to achieve lower voltage operation while keeping low the area and power overhead. The dynamic sleep design, which was developed at the 65nm node (Zhang et al., 2005), is further enhanced with op-amp-based active-feedback control and on-die programmable reference-voltage generator. The new sleep design reduces the effect of PVT variation, leading to further power reduction. The modular architecture of the design also enables the 16KB-subarray to be used directly as the building block for a 6MB L2 cache in the CoreTM 2 CPU (George, 2007). The design operates over 3.5GHz at 1.1V.

Published in:

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Date of Conference:

3-7 Feb. 2008