By Topic

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

22 Author(s)

A AAC-decoding, H.264 decoding, media processor with embedded forward-body-biasing and power-gating circuit in CMOS technology is proposed. Since all the components necessary for the scheme are simple MOS circuits requiring no extra supply voltages, they can be placed and routed by a commercial CAD tool. A data-mapping flip-flop was proposed as a high performance and low-power flip-flop. It is concluded that the power dissipation in H.264 720p 60fps decoding of 620mW at the process fast corner is the lowest among the processor-based solutions.

Published in:

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

Date of Conference:

3-7 Feb. 2008