A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS

High-speed low-resolution ADCs are an essential part of receivers for wireless standards such as UWB. These converters have to combine the stringent speed specifications with the demand for low power consumption. Flash architectures are often chosen because they offer the largest speed. However, in this architecture, area and power depend exponentially on the resolution since the comparators are often the largest contributor to the overall power consumption. Folding is a well-known technique used to reduce the number of comparators in an ADC while maintaining high speed. It was previously implemented by generating a number of zero crossings with folding amplifiers, often in combination with interpolation or averaging. In this design, a folding factor of 2 is realized as in but with only dynamic power consumption and without using amplifiers. This reduces the number of comparators from 31 to 16 for a 5b resolution.