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Performance of standard CMOS implementations has proved sufficient up to 60 GHz range and examples of operating blocks even beyond 60 GHz have been presented. Still, the choice of the receiver architecture entails several peculiar considerations in order to achieve a robust low-power solution. On the other hand, at high frequencies, to save power in both the VCO and dividers, it is desirable to synthesize a reference frequency that is lower than the received frequency. The authors have proposed a half-harmonic 24 GHz direct-conversion I/Q-receiver front-end with integrated multi-phase LO generation in 65 nm CMOS. Experiments show that adequate performance is achieved in a compact (2.1 mm2) low-power (below 100 mW) solution in an ultra- scaled RF CMOS process.