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In this paper, a CMOS implementation of phased-array receiver front-end, based on a widely tunable QVCO is presented. Each path achieves 30dB of gain and a minimum NF of 7.1dB, yielding a system NF of 4.1dB. The overall current draw is 54mA from a 1.2V supply. Additionally, a calibration procedure to mitigate the analog impairments imposed by the proposed implementation is demonstrated.
Published in:
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Date of Conference: 3-7 Feb. 2008
- Page(s):
- 184 - 605
- E-ISBN :
- 978-1-4244-2011-7
- Print ISBN:
- 978-1-4244-2010-0
- INSPEC Accession Number:
- 10047840
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2008.4523118
- Product Type:
- Conference Publications
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