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A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction Circuits

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6 Author(s)

This paper presents a CMOS image sensor integrating a 14b column-parallel cyclic ADC with on-chip digital error correction circuits. Column-parallel ADC arrays are located both above and below the pixel array. The area of the on-chip error-correction logic including memories for all the error coefficients of the 640 ADC channels is 0.85mmx7.9mm.

Published in:

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Date of Conference:

3-7 Feb. 2008