By Topic

Pipelined virtual camera configuration for real-time image processing based on FPGA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Seung Hun Jin ; School of Information and Communication Engineering, Sungkyunkwan University, Jangan-gu, Suwon, Gyeonggi-do, Korea ; Jung Uk Cho ; Jae Wook Jeon

Real-time image processing is important for many application areas which require a quick response from events in a scene. Since real-time image processing involves large amount of computations, many approaches have been proposed to solve this problem especially using a dedicated hardware system. However, they are not sufficiently adapted to practical use because their dedicated hardware architecture is not suitable to carry out multiple tasks even in the case of a reconfigurable architecture. This paper proposes a pipelined virtual camera configuration which can perform several image processing tasks, especially at the low and intermediate levels, through the reconfiguration of the system. By synchronizing the entire system with the pixel clock, each processing modules can regard the others as a virtual camera. As a result, both the performance and the degree of reconfiguration are significantly increased.

Published in:

Robotics and Biomimetics, 2007. ROBIO 2007. IEEE International Conference on

Date of Conference:

15-18 Dec. 2007