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VLSI Design of Diminished-One Modulo 2^{n}+1 Adder Using Circular Carry Selection

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2 Author(s)
Su-Hon Lin ; Grad. Sch. of Eng. Sci. & Technol., Nat. Yunlin Univ. of Sci. & Technol., Yunlin ; Ming-hwa Sheu

The diminished-one modulo 2n+1 addition is an important arithmetic operation for a high-performance residue number system. In this paper, we propose a new circular-carry-selection (CCS) technique for modulo 2n+1 addition in the diminished-one number domain. The architecture design of CCS modular adder is simple and regular for various bit-width inputs. For actual VLSI implementation, the proposed modular adder can demonstrate its superiority of savings up to 39.5% in AreaxTime and 46.3% in TimexPower performances over those of the previous existing solutions under 180-nm CMOS technology. Finally, the chip area and the clock rate of CCS diminished-one modulo 216+1 adder are 26746 mum2 and 476 MHz, respectively.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:55 ,  Issue: 9 )