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Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC

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4 Author(s)
Wei-Yin Chen ; DSP/IC Design Lab, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan ; Li-Fu Ding ; Pei-Kuei Tsung ; Liang-Gee Chen

High Definition (HD) video compression enables vivid reproduction of scenes. However, Motion Estimation (ME) requires large memory capacity and huge memory bandwidth, which are undesirable in many platforms including ASIC and SoC. In this paper, an algorithm and architecture design of cache system and fast ME in HD H.264/AVC are proposed. With the proposed cache system and hardware-oriented fast ME algorithm, the rate-distortion performance is maintained within 0.03dB difference, the size of on-chip memory reduced to only 10% to 21% of original size, while the external memory bandwidth from cache refill is also 18% to 56% less than that of level C data reuse scheme with vertical +64 search range.

Published in:

2008 IEEE International Conference on Acoustics, Speech and Signal Processing

Date of Conference:

March 31 2008-April 4 2008