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Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code

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5 Author(s)
Baraza, J.-C. ; Grupo de Sist. Tolerantes a Fallos (GSTF) of the Dept. de Inf. de Sist. y Comput. (DISCA), Univ. Politec. de Valencia (UPV), Valencia ; Gracia, J. ; Blanc, S. ; Gil, D.
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Deep submicrometer devices are expected to be increasingly sensitive to physical faults. For this reason, fault-tolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. First, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Second, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper, we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:16 ,  Issue: 6 )