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The nonlinearity of the input sampling switch in a switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage devices are unavailable. To address this issue, the use of an optimized bootstrapped CMOS switch is proposed in this paper. A linearized CMOS switch offers a constant on-resistance over the entire input signal range, greatly reducing track-mode distortion in a sampling circuit, compared to using a standard CMOS switch or a bootstrapped nMOS switch. The dynamic range improvement achieved as a result of the proposed technique is validated with the design of two high dynamic range fourth-order switched-capacitor DeltaSigma modulators for GSM and WCDMA radio standards in a 0.35-mum BiCMOS process technology. Measured spurious-free dynamic range (SFDR) of 86 and 77 dB at power consumptions of 7 and 14 mW, respectively, are achieved for GSM and WCDMA standards. Each modulator operates from a single 2.7-V power supply and occupies an area of 0.2 mm2 .