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Effect of noise on timing or data-pattern dependent delay variation when transmission-line effects are taken into account for on-chip wiring

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5 Author(s)
A. Deutsch ; IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, N.Y. 10598, USA ; H. H. Smith ; C. Vakirtzis ; J. Kozhaya
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The impact of data-pattern variation on timing for on-chip interconnect timing is investigated for typical local, global, and clock wiring. The validity of the methodology to combine noise and timing engines is benchmarked against accurate non-linear simulations with R(f)L(f)C circuit representation and recommendations for CAD tool development are given.

Published in:

Signal Propagation on Interconnects, 2007. SPI 2007. IEEE Workshop on

Date of Conference:

13-16 May 2007