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An important step in today's integrated circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also significantly increases IC layout file size. This has the undesirable side effect of increasing storage, processing, and I.O. times for subsequent steps of mask preparation. In this paper, we propose two techniques for compressing layout data, including OPC layout, while remaining compliant with existing industry standard formats such as OASIS and GDSII. Our approach is to eliminate redundancies in the representation of the geometrical data by finding repeating groups of geometries between multiple cells and within a cell. We refer to the former as ldquointercell subcell detection (InterSCD)rdquo and the latter as ldquointracell subcell detection (IntraSCD).rdquo We show both problems to be nondeterministic polynomial time hard (NP-hard), and propose two sets of heuristics to solve them. For OPC layout data, we also propose a fast compression method based on IntraSCD which utilizes the hierarchical information in the pre-OPC layout data. We show that the IntraSCD approach can also be effective in reconstructing hierarchy from flattened layout data. We demonstrate the results of our proposed algorithms on actual IC layouts for 90-nm, 130-nm, and 180-nm feature size circuit designs.
Date of Publication: May 2008