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This paper describes a common framework of test chip design for logic technology development and routine process monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The measurements of a set of transistor and process monitor test structures are reviewed and corresponding models discussed.
Date of Publication: May 2008