By Topic

An Industrial Case Study of Sticky Path-Delay Faults

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

Sticky path-delay faults are path delay faults that are neither robustly nor non-robustly testable, but cannot be proven functionally unsensitizable. Better characterization of delay test quality requires a proper analysis of sticky path-delay faults. Furthermore, careful elimination of sticky path-delay faults contributes significantly to test development productivity and reduction of delay test cost. We present an industrial case study that shows the following, (a) On average, even after designers have removed false paths using automated tools and manual overrides, about 8% of path-delay faults with slack less than 10% of the clock period can be sticky, (b) Our approach, which extends a previously proposed technique, identifies a large subset of sticky path-delay faults that cannot cause functional failures and hence can be eliminated from further consideration. This significantly refines the delay test quality assessment and test development effort, (c) Our approach significantly reprioritizes (reorders) the remaining paths for test generation thereby improving the quality of the target path list.

Published in:

VLSI Test Symposium, 2008. VTS 2008. 26th IEEE

Date of Conference:

April 27 2008-May 1 2008