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Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms

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4 Author(s)
Lisboa, C.A. ; Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre ; Argyrides, C. ; Pradhan, D.K. ; Carro, L.

For technologies beyond the 45 nm node, radiation induced transients will last longer than one clock cycle. In this scenario, temporal redundancy techniques will no longer be able to cope with radiation induced soft errors, while spatial redundancy techniques still impose high power and area overheads. The solution to this impasse is the use of algorithm level techniques, able to detect and correct errors with low cost. In this paper, a new approach to deal with this problem is proposed, and applied to matrix multiplication algorithm. The proposed technique is compared to previously published fault tolerance techniques, and the costs of detection and recomputation for both approaches are compared and discussed.

Published in:

VLSI Test Symposium, 2008. VTS 2008. 26th IEEE

Date of Conference:

April 27 2008-May 1 2008