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Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure

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3 Author(s)
Amin Chegeni ; Microelectronics Research Laboratory, Urmia University, Urmia, Iran. st ; Khayrollah Hadidi ; Abdollah Khoei

This paper presents a new structure of DRAM, using two-transistor cell. The most important advantages of this structure are: a) High speed read, write and refresh operation b) low data access latency c) low power consumption compared to other structures d) each write/refresh operation can be carried out just in one cycle and e) no need to special process and compatible with standard digital process.

Published in:

Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on

Date of Conference:

11-14 Dec. 2007