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CMOS Power Amplifier with ESD Protection Design Merged in Matching Network

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3 Author(s)
Yu-Da Shiu ; Ind. Technol. Res. Inst., Hsinchu ; Bo-Shih Huang ; Ming-Dou Ker

A power amplifier (PA) with combination of ESD protection circuit and matching network into single block was proposed and implemented in a 0.18-¿m CMOS process. By comprising ESD protection function into the matching network, this design omits individual I/O ESD clamps to alleviate loading that degrades RF performances. According to the experimental results, the ESD protection circuit with LC configuration contributes a 3.0-kV human body model (HBM) ESD robustness without significant degradation on RF performances of the PA for 2.4-GHz RF applications.

Published in:

Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on

Date of Conference:

11-14 Dec. 2007