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Mismatch and noise may impact the performance of integrated Bandgap voltage references. A usual solution to mitigate the impact of mismatch on performance is to include a trim circuit in the design. This technique results in more die area and longer test times. If the trim range is reduced, area and test time may be saved. Other factor that may also limit the performance of BGR circuits is the output noise, generated by integrated devices or from the supply voltage. Therefore, it is necessary to study how the output noise and variability due to process variations impact the design and applicability of trim circuits. Three BGR's were designed in a commercial 0.35 Â¿m CMOS technology, and its trim range and noise performance evaluated. Results show that in high-order BGRs, where the output noise is more relevant, the output noise must be properly accounted for in the design of the BGR and trim circuit. Simultaneous analysis of noise and mismatch leads to reduced trim range and proper prediction of the maximum precision that can be achieved.