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A 12-bit 43MHz switched capacitor pipelined analog-to-digital converter was implemented in a 0.5Â¿m 2P3M CMOS process based on 1.5-bit/stage architecture. The design features an on-chip continuous digital correction and a fully differential signal path circuitry that minimizes noise and relaxes comparator offset requirements. The design is a fully monolithic design that achieved an integral non-linearity of Â± 0.7 LSB and differential non-linearity of Â±0.8 LSB with power dissipation of 94mW.
Date of Conference: 11-14 Dec. 2007