A Pipelined 12-bit Analog-to-Digital Converter with Continuous On-Chip Digital Correction

A 12-bit 43MHz switched capacitor pipelined analog-to-digital converter was implemented in a 0.5¿m 2P3M CMOS process based on 1.5-bit/stage architecture. The design features an on-chip continuous digital correction and a fully differential signal path circuitry that minimizes noise and relaxes comparator offset requirements. The design is a fully monolithic design that achieved an integral non-linearity of ± 0.7 LSB and differential non-linearity of ±0.8 LSB with power dissipation of 94mW.