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SoC design and implementation for high reliable narrow-band power-line communications

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4 Author(s)
Sungsoo Choi ; Korea Electrotechnol. Res. Inst. (KERI), Ansan ; Won-Tae Lee ; Sungha Yun ; Young-chul Rhee

This paper describes a dual-mode type architecture for a high reliable narrow-band power-line communication (PLC) modem, and its design and implementation of a system-on-a-chip (SoC). The designed architecture is based on a chirp modulation technique for the purpose of overcoming time variations of power-line channel environments in the narrow-bandwidth of the frequency range of 95 - 148.5 kHz. The designed modem is fabricated utilizing a mixed 0.18 mum CMOS technology. Especially, according to the power-line channel environments the data transmission rate can be selectively changed into 2.5 kbps and 480 bps. The total hardware complexity of the implemented chip is about 50,000 gates, the power consumption is about 26 mW, and the operating frequency is up to 5.12 MHz.

Published in:

Power Line Communications and Its Applications, 2008. ISPLC 2008. IEEE International Symposium on

Date of Conference:

2-4 April 2008