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A novel high speed automatic layout system to place and route test structures for parametric test capability

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5 Author(s)
West, A.J. ; Nat. Semicond. Corp., Santa Clara, CA ; Mondal, S. ; Patra, D. ; Goswami, K.
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In this paper, we created a generalized framework for the automated placement and routing of analog test structures. We exploited the concept of terminal properties when placing and routing the test structures and generated a library of place and routing strategies for different architectures. This new approach significantly reduces layout time, maximizes the reuse of place and route routines, and facilitates the introduction of a holistic parametric test design flow.

Published in:

Microelectronic Test Structures, 2008. ICMTS 2008. IEEE International Conference on

Date of Conference:

24-27 March 2008

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