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A VLSI chip set for a multiprocessor workstation. II. A memory management unit and cache controller

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7 Author(s)
D. -K. Jeong ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; D. A. Wood ; G. A. Gibson ; S. J. Eggers
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For pt.I see ibid., vol.24, no.6, p.1688-98 (1989). The authors describe a memory management unit and a cache controller (MMU/CC) for a 40-70-MIPS multiprocessor workstation. The MMU/CC implements a novel memory management scheme, in-cache address translation, which does not require a translation lookaside buffer. It also implements a snooping bus protocol to maintain data consistency across all caches in the system. The chip is implemented in a 1.6-μm double-layer-metal CMOS technology and is being used in a multiprocessor workstation (SPUR) successfully executing a UNIX-like network-based operating system called Sprite as well as many applications, including LISP programs

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IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 6 )