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Trimming analog circuits using floating-gate analog MOS memory

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1 Author(s)
Carley, L.R. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100°C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 6 )

Date of Publication:

Dec 1989

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