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A Ta/Mo interdiffusion dual metal gate technology was successfully introduced to FinFET fabrication. The advantage of the proposed technology was examined by using the gate-first process without a metal-etch off step. The Ta/Mo gated nMOS FinFET with a reduced threshold voltage and the Mo gated pMOS FinFET exhibited symmetrical v alues of (0.31/0.36 V), which are desirable for the FinFET CMOS circuit operation with enhanced current drivability. It was also confirmed that the Ta/Mo interdiffusion process causes no degradation in the carrier mobility.
Date of Publication: June 2008