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A 3 \mu W CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation

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4 Author(s)
Holleman, J. ; Univ. of Washington, Seattle ; Bridges, S. ; Otis, B.P. ; Diorio, C.

This paper presents two novel hardware random number generators (RNGs) based on latch metastability. We designed the first, the DC-nulling RNG, for extremely low power operation. The second, the FIR-based RNG, uses a predictive whitening filter to remove nonrandom components from the generated bit sequence. In both designs, the use of floating-gate memory cells allows us to predict and compensate for DC offsets and other nonrandom influences while minimizing power consumption. We also present an efficient digital post-processing technique for improving randomness. We fabricated both RNGs in a standard 0.35 mum CMOS process. The DC-nulling RNG occupied .031 mm2 of die area, while the FIR-based RNG occupied 1.49 mm2.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 5 )