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Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

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3 Author(s)
Jin-Woo Han ; Sch. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon ; Chung-Jin Kim ; Choi, Yang-Kyu

A universal compact potential model for all types of double-gate MOSFETs is presented. An analytical closed-form solution to a 2D Poisson's equation is obtained with the approximation that a vertical channel potential distribution is a cubic function of position. As a result, an analytical equation for the threshold voltage is derived from the proposed potential model. Different gate work functions and independent gate biases for front and back gates are considered, and the proposed model is found to be valid for an arbitrary double-gate structure: a symmetric versus asymmetric double gate and a tied versus separated double-gate structure. The threshold voltage behaviors for double-gate MOSFETs are investigated for various device dimensions. The back-gate effects of the separated double gate are also investigated for various silicon channel thicknesses and gate oxide thicknesses. Last, a process-induced threshold voltage fluctuation is estimated for symmetric and asymmetric separated double-gate MOSFETs. The analytical solution of the threshold voltages is verified by a comparison with simulation results in terms of the gate length, the silicon thickness, and the gate oxide thickness. A good agreement between two sets of results is obtained.

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Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 6 )